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ltc1669 1 1669fa block diagram features applications description 10-bit rail-to-rail micropower dac with i 2 c interface the ltc ? 1669 is a 10-bit voltage output dac with true buffered rail-to-rail output voltage capability. it operates from a single supply with a range of 2.7v to 5.5v. the reference for the dac is selectable between the supply voltage or an internal bandgap reference. selecting the internal bandgap reference will set the full-scale output voltage range to 2.5v. selecting the supply as the reference sets the output voltage range to the supply voltage. the part features a simple 2-wire serial interface compat- ible with i 2 c that allows communication between many devices. the internal data registers are double buffered to allow for simultaneous update of several devices at once. the dac can be put in low current power-down mode for use in power conscious systems. power-on reset ensures the dac output is at 0v when power is initially applied, and all internal registers are cleared. the ltc1669 is pin-for-pin compatible with the ltc1663. for smbus-compatible designs, please refer to the ltc1663. differential nonlinearity (dnl) n micropower 10-bit dac in sot-23 n low operating current: 60a n ultralow power shutdown mode: 12a n 2-wire serial interface compatible with i 2 c ? n selectable internal reference or ratiometric to v cc n maximum dnl error: 0.75lsb n 8 user selectable addresses (msop package) n single 2.7v to 5.5v operation n buffered true rail-to-rail voltage output n power-on reset n 1.5v v il and 2.1v v ih for sda and scl n small 5-lead tsot-23 and 8-lead msop packages n digital calibration n offset/gain adjustment n industrial process control n automatic test equipment n arbitrary function generators n battery-powered data conversion products l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 10-bit dac latch input latch 2-wire interface sda ad0 (6) msop package only (2) (3) ad1 ad2 scl 1 (1) 5 (4) gnd 2 (7) v out 3 (8) 1669 bd v cc 1.25v 4 (5) bandgap reference reference select command latch note: pin numbers in parentheses refer to the msop package 10-bit buffered v out dac code 0 C1.0 error (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 156 512 640 1669 g02 C0.6 0.6 0.8 0.2 28 384 768 896 1024 v ref = v cc = 5v t a = 25 c
ltc1669 2 1669fa absolute maximum ratings v cc to gnd .............................................. ? 0.3v to 7.5v sda, scl ................................................. ?0.3v to 7.5v ad0, ad1, ad2 (msop only) ........ ?0.3v to (v cc + 0.3v) v out ............................................. ?0.3v to (v cc + 0.3v) (note 1) 1 2 3 4 sda ad1 ad2 scl 8 7 6 5 v out gnd ad0 v cc top view ms8 package 8-lead plastic msop t jmax = 125c,
ltc1669 3 1669fa electrical characteristics the denotes speci? cations which apply over the full operating tempera- ture range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v cc set as reference, v out unloaded, unless otherwise noted. symbol parameter conditions min typ max units dac resolution l 10 bits monotonicity (note 2) l 10 bits dnl differential nonlinearity guaranteed monotonic (note 2) l 0.2 0.75 lsb inl integral nonlinearity (note 2) l 0.5 2.5 lsb v os offset error measured at code 20 l 10 30 mv v ostc offset error temperature coef? cient 15 v/c fse full-scale error reference set to v cc reference set to internal bandgap l l 3 3 15 15 lsb lsb v out dac output span reference set to v cc reference set to internal bandgap 0 to v cc 0 to 2.5 v v v fstc full-scale voltage temperature coef? cient reference set to v cc reference set to internal bandgap 30 50 v/c v/c psrr power supply rejection ratio reference set to internal bandgap, code = 1023 0.4 lsb/v power supply v cc positive supply voltage l 2.7 5.5 v i cc supply current v cc = 3v (note 3) v cc = 5v (note 3) l l 60 75 100 125 a a i sd supply current in shutdown mode (note 3) l 12 24 a op amp dc performance short-circuit current (sourcing) v out shorted to gnd, input code = 1023 l 25 100 ma short-circuit current (sinking) v out shorted to v cc , input code = 0 l 30 120 ma output impedance to gnd input code = 0, v cc = 5v input code = 0, v cc = 5v in shutdown mode 65 150 500 1 1 k 1 output impedance to v cc input code = 1023, v cc = 5v input code = 1023, v cc = 5v 80 120 1 1 ac performance voltage output slew rate rising (notes 4, 5) falling (notes 4, 5) 0.75 0.25 v/s v/s voltage output settling time to 0.5lsb (notes 4, 5) 30 s digital feedthrough 0.75 nv?s digital-to-analog glitch impulse 1lsb change around major carry 70 nv?s digital inputs scl, sdas v ih high level input voltage l 2.1 v v il low level input voltage l 1.5 v v lt h logic threshold voltage 1.8 v i leak digital input leakage v cc = 5.5v and 0v, v in = gnd to v cc l 1 a c in digital input capacitance (note 7) l 10 pf digital output sda v ol digital output low voltage i pullup = 3ma l 0.4 v
ltc1669 4 1669fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: nonlinearity and monotonicity are de? ned from code 20 to code 1003 (full scale). see applications information. the denotes speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v cc set as reference, v out unloaded, unless otherwise noted. note 3: digital inputs at 0v or v cc . note 4: load is 10k in parallel with 100pf. note 5: v cc = v ref = 5v. dac switched between 0.1v fs and 0.9v fs , i.e., codes k = 102 and k = 922. note 6: all values are referenced to v ih and v il levels. note 7: guaranteed by design and not subject to test. symbol parameter min typ max units timing characteristics (notes 6, 7) f scl clock operating frequency 100 khz t buf bus free time between stop and start condition 4.7 s t hd, sta hold time after (repeated) start condition 4s t su, sta repeated start condition setup time 4.7 s t su, sto stop condition setup time 4s t hd, dat (in) data hold time (input) 0ns t hd, dat (out) data hold time (output) 225 500 3450 ns t su, dat data setup time 250 ns t low clock low period 4.7 s t high clock high period 4s t f clock, data fall time 20 300 ns t r clock, data rise time 20 1000 ns timing characteristics the denotes speci? cations which apply over the full operating tempera- ture range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v cc set as reference, v out unloaded, unless otherwise noted. symbol parameter conditions min typ max units address inputs ad0, ad1, ad2 (msop only) i up address pin pull-up current v in = 0v l 0.5 1.5 a v ih high level input voltage l v cc C 0.3 v v il low level input voltage l 0.8 v
ltc1669 5 1669fa integral nonlinearity (inl) differential nonlinearity (dnl) source and sink current capability with v cc = 5v large-signal step response midscale glitch load regulation vs output current code 0 C1.0 error (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 156 512 640 1669 g01 C0.6 0.6 0.8 0.2 28 384 768 896 1024 v ref = v cc = 5v t a = 25 c code 0 C1.0 error (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 156 512 640 1669 g02 C0.6 0.6 0.8 0.2 28 384 768 896 1024 v ref = v cc = 5v t a = 25 c output current source/sink (ma) 01 3 output voltage (v) 3.0 4.0 5.0 4.5 3.5 2.5 1.5 0.5 8 1669 g03 2.0 1.0 0 2 4 6 57 9 10 dac code = 1023 dac code = 0 t a = 25 c 5 5 0 4 3 2 v out (volts) sda (volts) 1 0 1669 g04 code = 990 code = 32 5 + s/div v cc = 5v r l = 4.7k c l = 100pf t a = 25 c 5v 0v v out 10mv/div sda 1669 g05 2 + s/div v cc = 5v r l = 4.7k c l = 100pf t a = 25 c code = 512 to 511 i out (ma) C4 C1.0 6 v out (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 C2 0 1 1669 g06 C0.6 0.6 0.8 0.2 C3 C1 2 3 4 v cc = v ref = 5v v out = 2.5v code = 512 t a = 25 c source sink typical performance characteristics load regulation vs output current offset error voltage vs temperature full-scale output voltage vs temperature i out (ma) C1.0 C1.0 6 v out (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 C0.6 C0.4 0 0.2 1669 g07 C0.6 0.6 0.8 0.2 C0.8 C0.2 0.6 0.4 0.8 1.0 v cc = v ref = 3v v out = 1.5v code = 512 t a = 25 c source sink temperature ( c) C60 offset error voltage (mv) 5 4 3 2 1 0 C1 C2 C3 C4 C5 C20 20 40 1669 g08 C40 0 60 80 100 temperature ( c) C60 output voltage (v) 2.510 2.508 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 C20 20 40 1669 g09 C40 0 60 80 100 reference set to internal bandgap
ltc1669 6 1669fa pin functions sda (pin 1, pin 1 on sot-23): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. high impedance pin while data is shifted in. open-drain n-channel output during acknowledgment. requires a pull-up resistor or current source to v cc . ad1 (pin 2): slave address select bit 1. tie this pin to either v cc or gnd to modify the corresponding bit of the ltc1669s slave address. ad2 (pin 3): slave address select bit 2. tie this pin to either v cc or gnd to modify the corresponding bit of the ltc1669s slave address. scl (pin 4, pin 5 on sot-23): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . v cc (pin 5, pin 4 on sot-23): power supply. 2.7v v cc 5.5v. also used as the reference voltage input when the part is programmed to use v cc as the reference. ad0 (pin 6): slave address select bit 0. tie this pin to either v cc or gnd to modify the corresponding bit of the ltc1669s slave address. gnd (pin 7, pin 2 on sot-23): system ground. v out (pin 8, pin 3 on sot-23): voltage output. buffered rail-to-rail dac output.
ltc1669 7 1669fa differential nonlinearity (dnl): the difference between the measured change and the ideal 1lsb change for any two adjacent codes. the dnl error between any two codes is calculated as follows: dnl = ( 6 v out C lsb)/lsb where 6 v out is the measured voltage difference between two adjacent codes. digital feedthrough: the glitch that appears at the ana- log output caused by ac coupling from the digital inputs when they change state. the area of the glitch is speci? ed in (nv)(sec). full-scale error (fse): the deviation of the actual full-scale voltage from ideal. fse includes the effects of offset and gain errors (see applications information). integral nonlinearity (inl): the deviation from a straight line passing through the endpoints of the dac transfer curve (endpoint inl). because the output cannot go below zero, the linearity is measured between full scale and the lowest code that guarantees the output will be greater than zero. the inl error at a given input code is calculated as follows: inl = [v out C v os C (v fs C v os )(code/1023)]/lsb where v out is the output voltage of the dac measured at the given input code. least signi? cant bit (lsb): the ideal voltage difference between two successive codes. lsb = v ref /1024 resolution (n): de? nes the number of dac output states (2 n ) that divide the full-scale range. resolution does not imply linearity. voltage offset error (v os ): nominally, the voltage at the output when the dac is loaded with all zeros. a single supply dac can have a true negative offset, but the output cannot go below zero (see applications information). for this reason, single supply dac offset is measured at the lowest code that guarantees the output will be greater than zero. definitions
ltc1669 8 1669fa timing diagram typical ltc1669 input waveformprogramming dac output for full scale (ad2 to ad0 set high) ack ack 123 address 456789123456789123456789123456789 full-scale voltage zero-scale voltage 1669 ta02 01001110 0 1 0 0 ad2 ad1 ad0 wr xxxxx000 xxxxxbgsdsy 11111111 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxx11 xxxxxxd9d8 ack stop start sda scl v out note: x = dont care ack command ls data ms data t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 1669 td t buf t low t high start condition repeated start condition stop condition start condition t r t f
ltc1669 9 1669fa applications information serial digital interface the ltc1669 communicates with a host (master) using the standard 2-wire interface. the timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus/i 2 c accelerator, are required on these lines. the ltc1669 is a receive-only (slave) device. the master can communicate with the ltc1669 using the quick com- mand, send byte or write word protocols as explained later. the start and stop conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica- tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has ? nished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock pulse. the slave-receiver must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. write word protocol the master initiates communication with the ltc1669 with a start condition and a 7-bit address followed by the write bit (wr) = 0. the ltc1669 acknowledges and the master delivers the command byte. the ltc1669 acknowledges and latches the command byte into the command byte input register. the master then delivers the least signi? cant data byte. again the ltc1669 acknowledges and the data is latched into the least signi? cant data byte input register. the master then delivers the most signi? cant data byte. the ltc1669 acknowledges once more and latches the data into the most signi? cant data byte input register. lastly, the master terminates the communication with a stop condition. on the reception of the stop condition, the ltc1669 transfers the input register information to output registers and the dac output is updated. slave address (msop package only) the ltc1669 can respond to one of eight 7-bit addresses. the ? rst 4 bits (msbs) have been factory programmed to 0100. the ? rst 4 bits of the ltc1669-8 have been factory programmed to 0011. the three address bits, ad2, ad1 and ad0 are programmed by the user and determine the lsbs of the slave address, as shown in the table below: ltc1669 ltc-1669-8 ad2 ad1 ad0 0100 xxx 0011 xxx l l l 0100 000 0011 000 l l h 0100 001 0011 001 l h l 0100 010 0011 010 l h h 0100 011 0011 011 h l l 0100 100 0011 100 h l h 0100 101 0011 101 h h l 0100 110 0011 110 h h h 0100 111 0011 111 write word protocol used by the ltc1669 command byte a slave address a wr lsdata byte a msdata byte a p s 81 71 1818 1669 ta03 11 1 s = start condition, wr = write bit = 0, a = acknowledge, p = stop condition
ltc1669 10 1669fa applications information slave address (sot-23 package) the slave address for the sot-23 package has been factory programmed to be 0100 000 (ltc 1669 ) and 0100 001 (ltc 1669 -1). if another address is required, please consult the factory. command byte 76543210 xxxxxbgsdsy sy 1 0 allows update on acknowledge of sync address only update on stop condition only (power-on default) sd 1 0 puts the device in power-down mode puts the device in standard operating mode (power-on default) bg 1 0 selects the internal bandgap reference selects the supply as the reference (power-on default) x x dont care the stop condition normally initiates the update of the dacs output latches. simultaneous update of more than one dac or other devices on the bus can be achieved by reissuing new start bit, address, command and data bytes before issuing a ? nal stop condition (which will update all the devices). an alternate way to achieve simultaneous ltc1669 updates is to override the stop condition update by setting the sy bit of the command byte. setting this bit sets the device to update the dac output latches only at the reception of a sync address quick command. the actual update occurs on the rising edge of scl during the acknowledge. in this way, all devices can update on the reception of the sync address quick command instead of the stop condition. a shutdown (sd) bit = high will put the device in a low power state but retain all data latch information. shutdown will occur at the reception of a stop condition. this way shutdown could be synchronized to other devices. the output impedance of the dac will go to a high impedance state ( 500k to gnd). the bandgap (bg) bit when set to 0 selects the dac supply voltage as its voltage reference. the full-scale output of the dac with this setting is equal to the supply voltage. when the bg bit is set to 1, the internal bandgap reference (1.25v) is selected as the dacs reference. the full-scale output voltage for this setting is 2.5v. data bytes least signi? cant data byte 76543210 d7 d6 d5 d4 d3 d2 d1 d0 most signi? cant data byte 76543210 xxxxxxd9d8 x = dont care send byte protocol the send byte protocol used on the ltc1669 is actually a subset of the write word protocol described previously. the send byte protocol can only be used to send the command byte information to the ltc1669. command byte a slave address a wr p s 811 71 1 1669 ta04 1 s = start condition, wr = write bit, a = acknowledge, p = stop condition the send byte protocol is also used whenever the write word protocol is interrupted for any reason. reception of a start or stop condition after the acknowledge of the command byte, but before the acknowledge of the last data byte, will cause both data bytes to be ignored and the command byte to be accepted. reception of a start or stop condition before the ac- knowledge of the command byte will cause the interrupted command byte to be ignored.
ltc1669 11 1669fa applications information sync address/quick command in addition to the slave address, the ltc1669 has an address that can be shared by other devices so that they may be updated synchronously. the address is called to the sync address and uses the quick command protocol. the sync address is 1111 110 ack stop start 1111 110 sy/clr 11 71 1669 ta05 1 sync address sy/clr 1 0 update output latches on rising edge of scl during acknowledge of sync address clear all internal latches on rising edge of scl during acknowledge of sync address the sy/clr bit set high only has meaning when the sy bit of the command byte was previously set high. on the otherhand, the sy/clr bit set low will always clear the part, independent of the state of the sy bit in the command byte. voltage output the output ampli? er contained in the ltc1669 can source or sink up to 5ma. the output stage swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 85 when driving a load to the rails. the output ampli? er is stable driving capacitive loads up to 1000pf. a small resistor placed in series with the output can be used to achieve stability for any load capacitance greater than 1000pf. for example, a 0.1f load can be driven by the ltc1669 if a 110 series resistance is used. the phase margin of the resulting circuit is 45 and increases monotonically from this point if larger values of resistance, capacitance or both are substituted for the values given. rail-to-rail output considerations as in any rail-to-rail device, the output is limited to volt- ages within the supply range. if the dac offset is negative, the output for the lowest codes limits at 0v as shown in figure 1b. similarly, limiting can occur near full scale when v cc is used as the reference. if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 1c. no full-scale limiting can occur if the internal reference is used. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. internal reference in applications where a predictable output is required that is independent of supply voltage, the ltc1669 has a user-selectable internal reference. selecting the internal reference will set the full-scale output voltage to 2.5v. this can be useful in applications where the supply voltage is poorly regulated. using the lt ? 1460 micropower series reference as a power supply for the ltc1669 in applications where the advantages of using the internal reference are required but the full-scale range needs to be greater than 2.5v, an external series reference can be used. the lt1460 is ideal for use as a power supply for the ltc1669 and can provide 3v, 3.3v and 5v full-scale output voltage ranges. the lt1460 provides accuracy, noise immunity and extended supply range to the ltc1669 when the ltc1669 is operated ratiometric to v cc . since both parts are available in sot-23 packages, the pc board space for this application is extremely small. see figure 2.
ltc1669 12 1669fa applications information figure 1. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for input codes near full scale when v ref = v cc 1669 f01 input code (b) output voltage negative offset 0v 512 0 1023 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse
ltc1669 13 1669fa applications information figure 2. lt1460 as power supply for the ltc1669 in 0.1 + f 1 5 (4) 1 (1) 2 4 (5) 2 (7) ltc1669 pin numbers in parentheses refer to msop package 3 (8) 3 3.9v to 20v 3v out to + p scl 1669 f02 v cc gnd sda out ltc1669 0v ) v out ) 3v gnd lt1460s3-3 0.01 + f +
ltc1669 14 1669fa s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635) 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 typ 5 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s5 tsot-23 0302 pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref package description
ltc1669 15 1669fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 0603 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
ltc1669 16 1669fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 1007 rev a ? printed in usa related parts typical application program up to 16 control outputs per bus and place them where they are needed + scl ad0 ad1 ad2 ltc1669cms8 v cc v out control output 0 0v ) v out0 < v cc 0.1 + f 0.1 + f 1 2 5 7 5 8 7 7 5 8 8 5 4 4 1 6 2 3 gnd + scl ad0 ad1 ad2 ltc1669cms8 v cc v out control output 1 0v ) v out1 < v cc 0.1 + f gnd + scl ad0 ad1 ad2 ltc1669-8cms8 v cc v out control output 15 0v ) v out15 < v cc 0.1 + f gnd 1669 ta06 smbus 1 ltc1694 smbus 2 gnd v cc v cc = 2.7v to 5.5v to other i 2 c devices + scl + p sda sda 1 4 6 2 3 sda 1 4 6 2 3 sda part number description comments ltc1694 smbus/i 2 c accelerator dual smbus accelerator with active ac and dc pull-up current sources ltc1694-1 smbus/i 2 c accelerator dual smbus accelerator with active ac pull-up current only dacs ltc1659 single rail-to-rail 12-bit v out dac in 8-lead msop package. v cc = 2.7v to 5.5v low power multiplying v out dac. output swings from gnd to ref. ref input can be tied to v cc . 3-wire interface. ltc1660/ltc1664 octal/quad 10-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v micropower rail-to-rail output. 3-wire interface. ltc1661 dual 10-bit v out in 8-lead msop package v cc = 2.7v to 5.5v micropower rail-to-rail output. 3-wire interface. ltc1663 10-bit v out in sot-23, smbus interface pin compatible with ltc1669 adcs ltc1285/ltc1288 8-pin so, 3v micropower adcs 1- or 2-channel, autoshutdown ltc1286/ltc1298 8-pin so, 5v micropower adcs 1- or 2-channel, autoshutdown

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